The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to fabrication methods and resulting structures for vertical field effect transistors having a strained channel region that includes an extension region configured and arranged to address defects associated with the channel region.
The metal oxide semiconductor field effect transistor (MOSFET) is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a metal oxide gate electrode. The metal gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”).
A type of MOSFET is a non-planar FET known generally as a vertical field effect transistor (VFET). VFETs employ semiconductor fins and side-gates that can be contacted outside the active region, resulting in increased device density and some increased performance over lateral devices. In VFETs, the source to drain current flows in a direction that is perpendicular to a major surface of the substrate. For example, in a known VFET configuration, a major substrate surface is horizontal, and a vertical fin extends upward from the substrate surface. The fin forms the channel region of the transistor. A source region and a drain region are situated in electrical contact with the top and bottom ends of the channel region, while a gate is disposed on one or more of the fin sidewalls. The introduction of strain into a VFET device would result in improved transistor performance.